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HIP2100
Data Sheet October 21, 2004 FN4022.13
100V/2A Peak, Low Cost, High Frequency Half Bridge Driver
The HIP2100 is a high frequency, 100V Half Bridge N-Channel power MOSFET driver IC. The low-side and high-side gate drivers are independently controlled and matched to 8ns. This gives the user maximum flexibility in dead-time selection and driver protocol. Undervoltage protection on both the low-side and high-side supplies force the outputs low. An on-chip diode eliminates the discrete diode required with other driver ICs. A new level-shifter topology yields the low-power benefits of pulsed operation with the safety of DC operation. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply.
Features
* Drives N-Channel MOSFET Half Bridge * SOIC, EPSOIC, QFN and DFN Package Options * SOIC, EPSOIC and DFN Packages Compliant with 100V Conductor Spacing Guidelines of IPC-2221 * Pb-Free Product Available (RoHS Compliant) * Bootstrap Supply Max Voltage to 114VDC * On-Chip 1 Bootstrap Diode * Fast Propagation Times for Multi-MHz Circuits * Drives 1000pF Load with Rise and Fall Times Typ. 10ns * CMOS Input Thresholds for Improved Noise Immunity * Independent Inputs for Non-Half Bridge Topologies
Ordering Information
PART # HIP2100IB HIP2100IBZ (Note 1) HIP2100EIB HIP2100EIBZ (Note 1) HIP2100IR HIP2100IRZ (Note 1) HIP2100IR4 HIP2100IR4Z (Note 1) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2. Add "T" suffix for Tape and Reel packing option. TEMP. RANGE (C) -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 PACKAGE 8 Ld SOIC PKG. DWG. # M8.15
* No Start-Up Problems * Outputs Unaffected by Supply Glitches, HS Ringing Below Ground, or HS Slewing at High dv/dt * Low Power Consumption * Wide Supply Range * Supply Undervoltage Protection * 3 Driver Output Resistance * QFN/DFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile
8 Ld SOIC (Pb-free) M8.15 8 Ld EPSOIC 8 Ld EPSOIC (Pb-free) 16 Ld 5x5 QFN 16 Ld 5x5 QFN (Pb-free) 12 Ld 4x4 DFN 12 Ld 4x4 DFN (Pb-free) M8.15C M8.15C L16.5x5 L16.5x5 L12.4x4A L12.4x4A
Applications
* Telecom Half Bridge Power Supplies * Avionics DC-DC Converters * Two-Switch Forward Converters * Active Clamp Forward Converters
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
HIP2100 Pinouts
HIP2100 (SOIC, EPSOIC) TOP VIEW
VDD HB HO HS 1 2 3 4 EPAD 8 7 6 5 LO VSS LI HI
HIP2100IR4 (DFN) TOP VIEW
HIP2100 (QFN) TOP VIEW
VDD NC NC 13 12 NC EPAD HO 3 NC 4 5 NC 6 HS 7 HI 8 NC 11 VSS 10 LI 9 NC LO 14
VDD NC NC HB HO HS
1 2 3 4 5 6 EPAD
12 LO 11 VSS 10 NC 9 8 7 NC LI HI NC 1 HB 2
16
15
NOTE: EPAD = Exposed PAD.
Application Block Diagram
+12V +100V
VDD HB
SECONDARY CIRCUIT
HI CONTROL PWM CONTROLLER LI
DRIVE HI
HO HS
DRIVE LO
LO
HIP2100 VSS
REFERENCE AND ISOLATION
2
FN4022.13
HIP2100 Functional Block Diagram
HB VDD UNDER VOLTAGE LEVEL SHIFT DRIVER HS HI HO
UNDER VOLTAGE DRIVER LI VSS
LO
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane.
+48V +12V
PWM
HIP2100
SECONDARY CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V +12V SECONDARY CIRCUIT
PWM
HIP2100
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
3
FN4022.13
HIP2100
Absolute Maximum Ratings
Supply Voltage, VDD, VHB-VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V Average Current in VDD to HB diode . . . . . . . . . . . . . . . . . . . 100mA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) SOIC (Note 5) . . . . . . . . . . . . . . . . . . . 95 N/A EPSOIC (Note 6) . . . . . . . . . . . . . . . . . 40 3.0 QFN (Note 6) . . . . . . . . . . . . . . . . . . . . 37 6.5 DFN (Note 6) . . . . . . . . . . . . . . . . . . . . 40 3.0 Max Power Dissipation at 25C in Free Air (SOIC, Note 5). . . . . . 1.3W Max Power Dissipation at 25C in Free Air (EPSOIC, Note 6) . . . 3.1W Max Power Dissipation at 25C in Free Air (QFN, Note 6) . . . . . . 3.3W Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55C to 150C Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . 300C For Recommended soldering conditions see Tech Brief TB389.
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . +9V to 14.0VDC Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS. . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES: 3. The HIP2100 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this mode of operation. 4. All voltages referenced to VSS unless otherwise specified. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. JC, the "case temp" is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C TJ = -40C TO 125C MAX MIN MAX UNITS
PARAMETERS SUPPLY CURRENTS VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating INPUT PINS Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Voltage Hysteresis Input Pulldown Resistance UNDERVOLTAGE PROTECTION VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis
SYMBOL
TEST CONDITIONS
MIN
TYP
IDD IDDO IHB IHBO IHBS IHBSO
LI = HI = 0V f = 500kHz LI = HI = 0V f = 500kHz VHS = VHB = 114V f = 500kHz
-
0.1 1.5 0.1 1.5 0.05 0.7
0.15 2.5 0.15 2.5 1 -
-
0.2 3 0.2 3 10 -
mA mA mA mA A mA
VIL VIH VIHYS RI
4 -
5.4 5.8 0.4 200
7 -
3 100
8 500
V V V k
VDDR VDDH VHBR VHBH
7 6.5 -
7.3 0.5 6.9 0.4
7.8 7.5 -
6.5 6 -
8 8 -
V V V V
4
FN4022.13
HIP2100
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) TJ = 25C PARAMETERS BOOT STRAP DIODE Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance LO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current HO GATE DRIVER Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current VOLH VOHH IOHH IOLH IHO = 100mA IHO = -100mA, VOHH = VHB-VHO VHO = 0V VHO = 12V 0.25 0.25 2 2 0.3 0.3 0.4 0.4 V V A A VOLL VOHL IOHL IOLL ILO = 100mA ILO = -100mA, VOHL = VDD-VLO VLO = 0V VLO = 12V 0.25 0.25 2 2 0.3 0.3 0.4 0.4 V V A A VDL VDH RD IVDD-HB = 100A IVDD-HB = 100mA IVDD-HB = 100mA 0.45 0.7 0.8 0.55 0.8 1 0.7 1 1.5 V V SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -40C TO 125C MIN MAX UNITS
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C MIN CL = 1000pF CL = 0.1F CL = IRFR120 CL = IRFR120 TYP 20 20 20 20 2 2 10 0.5 20 10 10 MAX 35 35 35 35 8 8 0.6 TJ = -40C TO 125C MIN MAX 45 45 45 45 10 10 0.8 50 UNITS ns ns ns ns ns ns ns us ns ns ns ns
PARAMETERS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) Upper Turn-Off Propagation Delay (HI Falling to HO Falling) Lower Turn-On Propagation Delay (LI Rising to LO Rising) Upper Turn-On Propagation Delay (HI Rising to HO Rising) Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On Either Output Rise/Fall Time Either Output Rise/Fall Time (3V to 9V) Either Output Rise Time Driving DMOS Either Output Fall Time Driving DMOS Minimum Input Pulse Width that Changes the Output Bootstrap Diode Turn-On or Turn-Off Time
SYMBOL tLPHL tHPHL tLPLH tHPLH tMON tMOFF tRC, tFC tR, tF tRD tFD tPW tBS
TEST CONDITIONS
5
FN4022.13
HIP2100 Pin Descriptions
SYMBOL VDD HB HO HS HI LI VSS LO EPAD DESCRIPTION Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB. High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-Side Output. Connect to gate of High-Side power MOSFET. High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-Side input. Low-Side input. Chip negative supply, generally will be ground. Low-Side Output. Connect to gate of Low-Side power MOSFET. Exposed Pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI, LI tHPLH , tLPLH HO, LO tHPHL, tLPHL
HI
LO tMON HO tMOFF
FIGURE 3.
FIGURE 4.
Typical Performance Curves
10 10
IDDO, IHBO (mA)
0.1
T = 150C T = 125C T = 25C T = -40C
IHBSO (mA)
1
1
T = 150C T = -40C T = 125C T = 25C
0.1
0.01 10
100 FREQUENCY (kHz)
1000
0.01 10
100 FREQUENCY (kHz)
1000
FIGURE 5. OPERATING CURRENT vs FREQUENCY
FIGURE 6. HB TO VSS OPERATING CURRENT vs FREQUENCY
6
FN4022.13
HIP2100 Typical Performance Curves
500 VHB = VDD = 9V 400 VOHL, VOHH (mV) VHB = VDD = 12V VOLL, VOLH (mV) VHB = VDD = 14V 300 400
(Continued)
500 VHB = VDD = 9V VHB = VDD = 12V VHB = VDD = 14V 300
200
200
100 -50
0
50 TEMPERATURE (C)
100
150
100 -50
0
50 TEMPERATURE (C)
100
150
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
7.6
0.54 0.5 VHBH, VDDH (mV) VDDR 0.46 0.42 0.38 VHBH 0.34 0.3 -50 VDDH
7.4 VHBR, VDDR (V)
7.2
7.0 VHBR 6.8
6.6 -50
0
50 TEMPERATURE (C)
100
150
0
50 TEMPERATURE (C)
100
150
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE
30 tLPLH, tLPHL, tHPLH, tHPHL (ns) tHPHL tHPLH 25 tLPHL IHO , ILO (A) tLPLH
2.5
2.0
1.5
1.0
20 0.5
15 -50
0 0 50 TEMPERATURE (C) 100 150
0
2
4
6 VHO , VLO (V)
8
10
12
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE
7
FN4022.13
HIP2100 Typical Performance Curves
2.5
(Continued)
1 0.1 FORWARD CURRENT (A) 0.01 0.001 1*10-4 1*10-5 1*10-6 0.3
2.0
ILO, IHO (A)
1.5
1.0
0.5
0
0
2
4
6 VLO, VHO (V)
8
10
12
0.4
0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT VOLTAGE
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
60 50 IHB vs VHB IDD , IHB (A) 40 IDD vs VDD 30 20 10 0 VHS TO VSS VOLTAGE (V)
120 100 80 60 40 20 0 12
0
5
10 VDD , VHB (V)
15
14 15 VDD TO VSS VOLTAGE (V)
16
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE
8
FN4022.13
HIP2100 Dual Flat No-Lead Plastic Package (DFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 A D D/2 D1 D1/2 2X N 0.15 C B C A
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 2.65 0.18 MIN 0.00 NOMINAL 0.85 0.01 0.65 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.80 4.00 BSC 3.75 BSC 1.43 1.58 0.50 BSC 0.635 0.30 0.40 12 6 0.24 0.42 0.60 12 0.50 1.73 2.95 0.30 MAX 0.90 0.05 0.70 NOTES 5, 8 7, 8 7, 8 8 2 3 Rev. 0 8/03
E1/2 E1 6 INDEX AREA 0.15 2X 0.15 2X 4X 0 A2 A C A C B 12 3
E/2 E
E
9
E1 E2
B
TOP VIEW
e k L
//
0.10 0.08 C
C
N Nd P
C SEATING PLANE
A3
A1
SIDE VIEW
7
8 D2
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. N is the number of terminals.
D2/2
(Nd-1)Xe REF.
1 6 INDEX AREA
23
3. Nd refer to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees.
NX k
5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
E2 7 8 E2/2
4X P N N-1 e NX b 0.10 5
M
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for the L dimension.
CA B
BOTTOM VIEW
C L NX b 5 CC e TERMINAL TIP A1
L
5
FOR EVEN TERMINAL/SIDE
9
FN4022.13
HIP2100 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHB ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 4 0.25 0.35 2.55 2.55 0.28 MIN 0.80 NOMINAL 0.90 0.20 REF 0.33 5.00 BSC 4.75 BSC 2.70 5.00 BSC 4.75 BSC 2.70 0.80 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.85 2.85 0.40 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
10
FN4022.13
HIP2100 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 0o MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0o
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 8o
A1 B C D E e
C

A1 0.10(0.004)
e
B 0.25(0.010) M C AM BS
0.050 BSC
1.27 BSC
H h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
11
FN4022.13
HIP2100 Small Outline Exposed Pad Plastic Packages (EPSOIC)
N INDEX AREA H E -B1 2 3 0.25(0.010) M BM
M8.15C
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD PLASTIC PACKAGE INCHES SYMBOL A A1 B
L SEATING PLANE -AD -CA h x 45o
MILLIMETERS MIN 1.43 0.03 0.35 0.19 4.80 3.811 5.84 0.25 0.41 8 8o 0o 8o 3.200 2.514 MAX 1.68 0.13 0.49 0.25 4.98 3.99 6.20 0.41 0.89 NOTES 9 3 4 5 6 7 11 11 Rev. 0 11/03
MIN 0.056 0.001 0.0138 0.0075 0.189 0.150 0.230 0.010 0.016 8 0o -
MAX 0.066 0.005 0.0192 0.0098 0.196 0.157 0.244 0.016 0.035
TOP VIEW
C D E e H h L
C
0.050 BSC
1.27 BSC

A1 0.10(0.004)
e
B 0.25(0.010) M SIDE VIEW C AM BS
N
P P1 NOTES:
0.126 0.099
1
2
3
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11. Dimensions "P" and "P1" are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size.
N P BOTTOM VIEW
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN4022.13

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